The present invention relates generally to semiconductor memories, and more particularly to a semiconductor device having two memory portions that are connected by a transfer bus of reduced size.
Many computer systems can include a main memory. In order to maintain reasonable costs in such computer systems, main memories are typically composed of dynamic random access memories (DRAMs). DRAMs can be fabricated in a variety of configurations and sizes. In the past, general purpose (asynchronous) DRAMs could provide sufficient speed at a low enough cost to be used in a main memory.
More recently, however, computer operating speeds have begun to outpace the speed of general purpose DRAMS. In particular, processor speeds have outpaced the data transfer rates of general purpose DRAMs. To alleviate the disparities in processor rates and general purpose DRAM data transfer rates, many systems have employed a substorage device situated between a main memory and a processor. Such substorage devices are typically referred to as xe2x80x9ccachexe2x80x9d memories. A cache memory is typically a high-speed memory device, such as a static RAM (SRAM) or an emitter coupled logic bipolar RAM (ECLRAM), to name just a few examples. A cache memory can be integrated into a processor, or may be provided external to the processor.
Another variation in memory devices combines DRAMs and high speed cache-type RAMs on the same device. Such combination devices have been utilized in computer workstations and some personal computers. Such devices can include a main storage formed from a DRAM and a cache memory formed from a SRAM. Both the DRAM and SRAM are formed on the same semiconductor substrate. Such devices have been referred to as cache DRAMs or CDRAMs.
CDRAMs can be arranged to transfer data between the DRAM and SRAM portions in a bidirectional fashion. When a memory is accessed, if the requested data location is in the SRAM portion, the access can be considered a cache xe2x80x9chit.xe2x80x9d If a requested data location is not in the SRAM portion, the access can be considered a cache xe2x80x9cmiss.xe2x80x9d The requested data can then be retrieved from the DRAM. A drawback to conventional CDRAMs is that cache misses can introduce some delay into a data transfer operation.
Another drawback to such CDRAMs is the number of external pins that are utilized in such devices (pin count). Because the DRAM portion and SRAM portion have their own respective address pins, the number of pins on a CDRAM can be much larger than those of a conventional DRAM. Therefore, a CDRAM device is not easily utilized with typical DRAM controllers.
Yet another problem associated with conventional CDRAMs is the amount of area that may be needed to realize a data transfer circuit. Because the area available for such circuits can be limited, the number of transfer bus lines between a DRAM and SRAM portion can also be limited.
Due to the above constraints, the number of data bits that can be transferred at the same time between a DRAM portion and a SRAM portion on a CDRAM can be limited. Further, many conventional CDRAM approaches avoid placing transfer lines in the same area as column select lines. As a result, the number of transfer lines can further be limited by the width of such available areas. As a general rule, the smaller the number of bits that can be transferred between DRAM and SRAM portions, the lower hit rate of the cache. One skilled in the art would recognize that lower cache hit rates leads to slower overall data access operations for a CDRAM.
The current applicant has previously proposed a xe2x80x9cvirtual channelxe2x80x9d memory. In particular, a virtual channel synchronous DRAM (VCSDRAM) has been disclosed in Japanese Patent Publication No. Hei 11-86559 that can increase the access speed of a SDRAM.
The above-described VCSDRAM can include a memory array of DRAM cells arranged into rows and columns. In addition to the memory array, the VCSDRAM can include a register array having a number of rows and columns. The number of rows and/or columns in the register array can be some ratio of the number of rows and/or columns in the memory array. The register array can provide a cache function in the row and or column directions, and can include SRAM cells.
The above-described VCSDRAM can have a number of applications. One particular advantageous application of a VCSDRAM is the storing and/or displaying of video data. Data can be stored within a memory cell as picture elements (pixels). Pixel data can then be read out in a successive fashion from the same region of the memory array. The pixel data can be amplified by a sense amplifier group corresponding to the memory array region. Particular sense amplifiers can then be selected to transfer data to the channel register by way of a transfer bus.
Referring now to FIG. 6, a VCSDRAM, such as that referred to above, is illustrated in a block diagram. The VCSDRAM is designated by the general reference character 600, and is shown to include two cell regions, designated as 602-0 and 602-1. The cell regions (602-0 and 602-1) can include a number of memory cells connected to digit lines, one of which is shown as 604. As just one arrangement, the digit lines can be connected to memory cells in a column-wise direction.
A number of sense amplifiers, one of which is shown as item 606, are situated adjacent to both cell regions (602-0 and 602-1). Sense amplifier 606 (and those sense amplifiers within its group) can be considered xe2x80x9ccornmonxe2x80x9d to both cell regions (602-0 and 602-1). At the other end of cell region 602-0 is another group of sense amplifiers, one of which is shown as item 608. Further, at the other end of cell region 602-1 is a third group of sense amplifiers, one of which is shown as item 610. In the arrangement of FIG. 6, sense amplifier 608 (and those sense amplifiers within its group) is dedicated to cell region 602-0, and sense amplifier 610 (and those sense amplifiers within its group) is dedicated to cell region 602-1.
The VCSDRAM 600 further includes a number of registers 614-0 to 614-2 disposed at one end of the cell regions (602-0 and 602-1). The registers (614-0 to 614-2) can be connected to the various sense amplifier groups by transfer bus lines, shown as 616-00 to 616-21. Connections between the sense amplifiers and their associated transfer bus lines (616-00 to 616-21) can be conventional in nature, and are not shown in particular in FIG. 6.
For example, transfer bus lines 616-20/21 can transfer data from sense amplifier 606, 608 or 610 to channel register 614-2. That is, one sense amplifier group can be activated, and thereby place data on the transfer bus lines (616-00 to 616-21) and into registers (614-0 to 614-2). Data stored in registers (614-0 to 614-2) can be transferred to external locations according to channel read and channel write commands.
In the arrangement of FIG. 6, signals SSU1, SSU2, SSM1, SSM2, SSD1 and SSD2 indicate sense amplifier selection signals. Sense amplifier selection signals can be applied to sense amplifier groups by way of select lines, shown as 618-00/01, 618-10/11, and 618-20/21. In the arrangement of FIG. 6, sense amplifier groups can be conceptualized as including xe2x80x9cevenxe2x80x9d sense amplifiers that alternate with xe2x80x9coddxe2x80x9d sense amplifiers. Accordingly, select signal SSU1 can select even sense amplifiers from the group that includes sense amplifier 608, and select signal SSU2 can select odd sense amplifiers. Along these same lines, select signal SSM1 can select even sense amplifiers and SSM2 can select odd sense amplifiers from the group that includes sense amplifier 606, and select signal SSD1 can select even sense amplifiers and SSD2 can select odd sense amplifiers from the group that includes sense amplifier 610.
Referring once again to FIG. 6, when the SSU1 signal is activated, sense amplifier 608 can place data on transfer lines 616-20/21. However, if the SSU2 signal is activated, the sense amplifier to the left of sense amplifier 608 can place data on transfer lines 616-20/21. Data on transfer lines 616-20/21 can be stored in channel register 614-2.
It can be understood from the above description that in the arrangement of FIG. 6, when a cell region (such as 602-0 or 602-1) is accessed, data from one of four sense amplifiers will be placed on a given transfer line. In particular, in FIG. 6, when cell region 602-0 is accessed, data will be placed on transfer lines 616-20/21 according to whether select signal SSU1, SSU2, SSM1 or SSM2 is activated.
A drawback to the arrangement of FIG. 6 is that a pair of transfer lines (616-00/01 to 616-20/21) is provided for every two sense amplifiers in a row. It may be difficult and/or inefficient to form transfer lines with such a periodicity (i.e., pitch).
Another drawback to the arrangement of FIG. 6 is that for speed and/or power purposes, the data signal carried on transfer lines (616-00 to 616-21) can have a relatively small amplitude. Consequently, to minimize disturbing such a data signal it may be necessary in some cases to employ shielding conductors 620. Shielding conductors 620 can reduce xe2x80x9ccrosstalkxe2x80x9d between adjacent transfer line pairs (616-00/01 to 616-20/21). Accordingly, the use of such shielding conductors can further increase line pitch, as three lines are provided for every two sense amplifiers in a row.
As semiconductor manufacturing processes advance, it can be possible to decrease device sizes, resulting in reductions in storage device (such as memory cells and registers) and sense amplifier size. However, it may not always be possible to reduce conductive line (xe2x80x9cwirexe2x80x9d) size, particularly if the conductive line is formed from a higher level of metallization. As a result, while device sizes decrease, structures that include a number of conductive lines may not scale down correspondingly. This may be particularly true for buses, such as a transfer bus in a memory device like a VCSDRAM.
It would be desirable to provide a semiconductor device that includes two memory portions (such as a DRAM and SRAM portion) joined by a transfer bus having a decreased number of transfer bus lines. It would also be desirable for such a reduced-bus size semiconductor device to maintain a relatively high data transfer rate. It would be further desirable for such a semiconductor device to be a VCSDRAM.
An object of the present invention to provide a semiconductor device having a first memory portion connected to a second memory portion with a transfer bus having a reduced number of bus lines. Even with such a reduced bus size, the semiconductor device can maintain a relatively high data processing speed for image processing, or the like.
To achieve the above-mentioned object, a semiconductor memory according to one embodiment of the present invention can include a memory cell array having a number of cell regions disposed in a first direction, sense amplifiers corresponding to each cell region, and a transfer bus extending in the first direction over the cell regions. The transfer bus can include a number switch circuits, each switch circuit corresponding to a cell region. The switch circuits can divide the transfer bus into a number of transfer bus portions.
In the above-described arrangement it can be possible to transfer data on multiple transfer bus portions created by dividing the transfer bus. In this way the efficiency of the transfer bus can be improved without increasing the overall number of transfer bus lines. Further, the number of registers (i.e., the size of second memory portion) can be increased.
In particular, one transfer bus (divided by a switch circuit) can be shared by channel registers. This can allow the number of registers to be doubled while maintaining essentially the same data processing speed.
It is understood that while the present invention may be advantageously employed in a virtual channel synchronous dynamic random access memory (VCSDRAM), the invention should not be construed as being limited to such a particular application. Further, the various general portions described, such as a transfer bus, register and memory cell region, should not be limited. Structures for other conventional semiconductor memories can be used for these portions.
In a preferred arrangement, channel registers are situated at both ends of a transfer bus. In this way, each channel register can transfer data to and from a memory cell via a transfer bus portion.
Also in a preferred arrangement, a transfer bus can include a transfer bus line divided into a number of transfer bus line portions. A sense amplifier group can be associated with each transfer bus line portion. Data can be placed on a transfer bus line portion by activating one sense amplifier of the corresponding sense amplifier group.
Furthermore, in a preferred arrangement, switching circuits are turned off before a memory cell in a corresponding memory cell array is selected. This operation can reduce interference between multiple memory cell arrays.
Furthermore, in a preferred arrangement, a group of sense amplifiers can be common to two memory cell arrays. The group of sense amplifiers can be situated between its corresponding arrays, reducing the space consumed by the group of sense amplifiers.
Furthermore, in a preferred arrangement, a switching circuit can have a number of switch banks, a memory array can have a number of array banks, and the channel registers can be arranged into a number of channel register portions. The switching circuit can be turned off in response to a number of commands. Two such commands include a prefetch instruction which can transfer data from a sense amplifier to a channel register, and a restore command that can transfer data from a channel register to a sense amplifier. In such an arrangement, data can be transferred from multiple array banks to corresponding multiple channel register portions over transfer bus portions created by the switch banks.